1. Field of the Invention
The present invention relates to an analysis method of film thickness distribution and a design system of printed circuit boards and manufacturing processes in the process of using pattern plating method for forming a plated film on a circuit pattern on a selective basis where a printed circuit board is formed by electroplating.
2. Prior Art
With recent increase in LSI speed and density, there has been a growing demand for lines of smaller size and greater number of multilayers in the printed circuit board for implementation of a semiconductor and mobile equipment.
In the prior art, subtractive process has been widely employed to form lines on the printed circuit board. In the subtractive process, metal is formed (by panel plating) on the entire surface of the substrate by electroplating, and unwanted part of the line is removed by etching, whereby lines are formed on the printed circuit board. However, the subtractive process requires the etching of a metal having a thickness on the order of 10 μm. This necessarily requires the side wall of the metal interconnecting line be etched, and formation of a fine interconnecting line and space is accompanied by difficulties. The maximum permissible size has been about 50 μm in interconnecting line and space width.
Under these circumstances described above, additive process has come to be used in recent years in order to provide a finer line on the printed circuit board. In the additive process, a circuit pattern is formed on a printed circuit board by a resist, and metal is then formed (by pattern plating) only on the circuit pattern by electroplating on a selective basis. According to this process, the metal line aspect ratio is almost the same as the resolution of resist, so this process is suited for formation of a fine line.
The additive process is available in three types of processes—full-additive, semi-additive and partly additive—depending on the difference in the processes before and after electroplating. In any of these process types, metal is formed only on the circuit pattern in the electroplating process on a selective basis.
In the pattern plating process, film is formed only on the circuit pattern, so a big imbalance occurs to the distribution of film thickness, depending on the density of the interconnecting line and arrangement of the chip (located at the center of the plated surface or at the end). A big imbalance in the distribution of film thickness will result in reduced yields and reliability. Further, it becomes difficult to increase the number of layers.
Optimization of the circuit pattern and improvement of the plating unit are required to ensure uniformity in the distribution of film thickness. Much development cost and time period are required in the case of experiment alone. Such being the case, there has been a long felt need for prediction of film thickness distribution by computer simulation.
The prior art includes the following electroplating film thickness analysis program by computer simulation:
“Electro-Plating Pilot System” by Uemura Industry {HYPERLINK“http://www.uemura.co.jp/uemura/epps/index.html”, http://www.uemura.co.jp/uemura/epps/index.html}
Case Western Revers Univ. Cell Design http://www.L-Chem.com
According to the simulation process by electric field analysis using these prior art finite element method and boundary element method, massive amounts of meshes (ex. 1010 meshes) have been required to simulate an actual product with an extra-small width line (within several μm) present on a substrate of scores of square centimeters. Calculation has been very difficult.